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Цифро-аналоговые преобразователи фирмы Texas Instruments
Digital-to-analog converters Texas Instruments |
| DACs (< 10MHz) Family | |||||||||||
| Device Name |
Reso- lution Bits |
Supply V |
Data- Bus Inter- face bits |
Settling Time us |
# of DAC |
Power typ mW |
Output I or V |
Vref | DNL max ±LSB |
INL max ±LSB |
Comments |
| UCC5950 Unitrode |
10 | 5 | 2.5 | 1 | 7.5 | V | 1 | 2 | 10-Bit Serial D/A Converter with Sleep Mode | ||
| TLV5639 | 12 | 2.7 to 5.5 | P12 | 1 | 1 | 2.7 | V | Int | 0.5 | 3 | Programmable: Int Ref, pwr consumption, settling time; SNR 78dB, SFDR -74 dB@fout=1kHz |
| TLV5638 | 12 | 2.7 to 5.5 | Ser | 1 | 2 | 4.5 | V | Int | 1 | 4 | Simultaneous Dual DAC Update; Programmable: Int Ref, pwr consumption, settling time; SNR 78dB, SFDR -74dB@fout=1kHz |
| TLV5637 | 10 | 2.7 to 5.5 | Ser | 1 | 2 | 4.2 | V | Int | 0.5 | 1 | Programmable: int ref, pwr consumption, settling time; SNR 56dB, SFDR -62dB@fout=1kHz |
| TLV5636 | 12 | 2.7 to 5.5 | Ser | 1 | 1 | 4.5 | V | Int | 1 | 4 | Programmable: Int Ref, pwr consumption, settling time; SNR 75dB, SFDR -69dB@fout=1kHz |
| TLV5633 | 12 | 2.7 to 5.5 | P8 | 1 | 1 | 2.7 | V | Int | 0.5 | 3 | Programmable: Int Ref, pwr consumption, settling time; SNR 78dB, SFDR -74dB@fout=1kHz |
| TLV5628 | 8 | 2.7 to 5.5 | Ser | 10 | 8 | 12 | V | Ext | 0.9 | 1 | Octal; Programmable for 1x or 2x Output; Simultaneous update |
| TLV5627 | 8 | 2.7 to 5.5 | Ser | 3 | 4 | 3 | V | Ext | 0.5 | 0.5 | Programmable: pwr consumption, settling time; SNR 57dB, SFDR -60dB@fout=1.1kHz |
| TLV5626 | 8 | 2.7 to 5.5 | Ser | 1 | 2 | 5.1 | V | Int | 0.5 | 1 | Programmable: int ref, pwr consumption, settling time; SNR 57dB, SFDR -62dB@fout=1kHz |
| TLV5625 | 8 | 2.7 to 5.5 | Ser | 2.5 or 12 | 2 | 2.1 | V | Ext | 0.2 | 0.5 | Programmable: pwr consumption, settling time; SNR 54dB, SFDR -50dB@fout=1kHz |
| TLV5624 | 8 | 2.7 to 5.5 | Ser | 1.0 to 3.5 | 1 | 4.5 | V | Int | 0.2 | 0.5 | Programmable: int ref, pwr consumption, settling time; SNR 57dB, SFDR -62dB@fout=1kHz |
| TLV5623 | 8 | 2.7 to 5.5 | Ser | 3 | 1 | 0.9 | V | Ext | 0.2 | 0.5 | Programmable: pwr consumption, settling time; SNR 57dB, SFDR -60dB@fout=1.1kHz |
| TLV5621 | 8 | 2.7 to 5.5 | Ser | 10 | 4 | 3.6 | V | Ext | 0.9 | 1 | Simple two-wire interface in single-buffered mode; Simultaneous update in double-buffered mode; one very low pwr DAC |
| TLV5620 | 8 | 2.7 to 5.5 | Ser | 10 | 4 | 6 | V | Ext | 0.9 | 1 | Simultaneous -update Quad; Programmable 1x or 2x Out Range |
| TLV5619 | 12 | 2.7 to 5.5 | P12 | 1 | 1 | 4.3 | V | Ext | 1.0 | 4 | Asynchronous Update; SNR 78dB, SFDR -72dB@fout=1kHz |
| TLV5618A | 12 | 2.7 to 5.5 | Ser | 2.5 | 2 | 2.4 | V | Ext | 1 | 4 | Programmable: pwr consumption, settling time; SNR 76dB, SFDR -72dB@fout=1kHz |
| TLV5617A | 10 | 2.7 to 5.5 | Ser | 2.5 | 2 | 2.1 | V | Ext | 1.0 | 1 | Programmable: pwr consumption, settling time; SNR 56dB, SFDR -64dB@fout=1kHz |
| TLV5616 | 12 | 2.7 to 5.5 | Ser | 3 | 1 | 0.9 | V | Ext | 1.0 | 4 | Programmable pwr consumption; Super small MSOP-8 package; SNR 74dB@fout=1.1kHz |
| TLV5614 | 12 | 2.7 to 5.5 | Ser | 3 | 4 | 3.6 | V | Ext | 1.0 | 4 | Simultaneous Quad DAC update; Programmable pwr consumption; Independent digital/analog supplies |
| TLV5613 | 12 | 2.7 to 5.5 | P8 | 1 | 1 | 1.2 | V | Ext | 1.0 | 4 | Programmable pwr consumption; Separate digital/analog supplies; Synchronous/Asynchronous update |
| TLV5606 | 10 | 2.7 to 5.5 | Ser | 3/9 | 1 | 0.9 | V | Ext | 1.0 | 1.5 | 8-pin MSOP, Programmable Speed, High-Speed Serial Interface, 5V/3V Single Supply, Voltage-Output Buffer, Power-Down Mode |
| TLV5604 | 10 | 2.7 to 5.5 | Ser | 3 | 4 | 3.3 | V | Ext | 0.5 | 0.5 | Simultaneous Quad DAC update; Programmable pwr consumption; Separate digital/analog supplies |
| TLC7628 | 8 | 11 to 15 | Par | 0.1 | 2 | 20 | I | Ext | 0.5 | 0.5 | Dual Multiplying DAC; TTL-compatible; super easy micro interface |
| TLC7528 | 8 | 5 to 15 | Par | 0.1 | 2 | 7.5 | I | Ext | 0.5 | 0.5 | Dual TLC7524 (Multiplying DAC) |
| TLC7524 | 8 | 5 to 15 | Par | 0.1 | 1 | 5 | I | Ext | 0.5 | 0.5 | MDAC; Fast Control Signaling; Low Glitch Output; on-chip data latches; super easy micro interface |
| TLC7226 | 8 | 15 | Par | 5 | 4 | 60 | V | Ext | 1 | 1 | Quad Multiplying DAC; Single or dual supply; TTL/CMOS compatible |
| TLC7225 | 8 | 5 to 15 | Par | 5 | 4 | 60 | V | Ext | 1 | 1 | Quad; Single or dual supply; Direct bipolar operation without an external level-shift amplifier; TTL/CMOS compatible |
| TLC5628 | 8 | 5 | Ser | 10.0 | 8 | 15 | V | Ext | 0.9 | 1 | Octal; Programmable for 1x or 2x Output; Simultaneous update |
| TLC5620 | 8 | 5 | Ser | 10.0 | 4 | 8 | V | Ext | 0.9 | 1 | Quad; Programmable 1x or 2x output range |
| TLC5618A | 12 | 5 | Ser | 2.5 | 2 | 3 | V | Ext | 1 | 4 | Simultaneous Dual DAC update; Programmable pwr consumption |
| TLC5617A | 10 | 5 | Ser | 2.5 | 2 | 3 | V | Ext | 0.5 | 1 | Simultaneous Dual DAC update; Programmable pwr consumption |
| TLC5615 | 10 | 5 | Ser | 12.5 | 1 | 0.75 | V | Ext | 0.5 | 1 | 1.21 MHz Update Rate; SINAD 60dB@1kHz |
| DACs (>= 10MHz) Family | |||||||||
| Device Name |
Reso- lution Bits |
Supply V |
Update Rate MSPS |
Sett- ling Time ns |
# of DAC |
Power typ mW |
DNL max ±LSB |
INL max ±LSB |
Comments |
| TLC5602 | 8 | 5 | 30 | 30 | 1 | 80 | 0.5 | 0.5 | TTL digital input voltage |
| TL5632 | 8 | 5 | 60 | 10 | 3 | 350 | 0.5 | 0.5 | High performance at lowest cost for high speed system |
| THS8134B | 8 | 3.0 to 5.0 | 80 | 5 | 3 | 635 | 1.2 | 1 | SMPTE compliant Tri-level Sync generation, Multiplexed YPbPr/GBR input mode |
| THS8134A | 8 | 3.0 to 5.0 | 80 | 5 | 3 | 525 | 1.2 | 1 | SMPTE compliant Tri-level Sync generation, Multiplexed YPbPr/GBR input mode |
| THS8134 | 8 | 3.0 to 5.0 | 80 | 5 | 3 | 525 | 1.2 | 1 | SMPTE compliant Tri-level Sync generation, Multiplexed YPbPr/GBR input mode |
| THS8133A | 10 | 3.0 to 5.0 | 80 | 5 | 3 | 525 | 1.2 | 1 | SMPTE compliant Tri-level Sync generation, Multiplexed YPbPr/GBR input mode |
| THS8133 | 10 | 3.0 to 5.0 | 80 | 5 | 3 | 525 | 1.2 | 1 | SMPTE compliant Tri-level Sync generation, Multiplexed YPbPr/GBR input mode |
| THS5671A | 14 | 3.0 to 5.0 | 125 | 35 | 1 | 175 | 0.50 | 0.75 | CommsDAC; 81dBc SFDR @ f(clk)=25MSPS,f(out)=1MHz; |
| THS5661A | 12 | 3.0 to 5.0 | 125 | 35 | 1 | 175 | 2.0 | 4.0 | CommsDAC; 76 dBc SFDR @ f(clk) = 25MSPS, f(out)=1M |
| THS5651A | 10 | 3.0 to 5.0 | 125 | 35 | 1 | 175 | 0.5 | 1 | CommsDAC; 79 dBc SFDR @ f(clk)=25MSPS, f(out)=1MHz; Binary or 2s complement input modes |
| THS5641A | 8 | 3.0 to 5.0 | 100 | 35 | 1 | 100 | 0.5 | 1 | CommsDAC; 66 dBc SFDR @ f(clk) = 25MSPS, f(out)=1MHz; ; Binary or 2s complement input modes |
| THS5641 | 8 | 3.0 to 5.0 | 100 | 35 | 1 | 100 | 0.5 | 1 | CommsDAC; 66 dBc SFDR @ f(clk) = 25MSPS, f(out)=1MHz; ; Binary or 2s complement input mode; |
